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Nuno Miguel Paulino
Assistant Researcher
I received my Master's Degree from FEUP (Faculdade de Engenharia da Universidade do Porto), in Electrical and Computer Engineering. My thesis was titled Generation of Reconfigurable Circuits from Machine Code, a work which continued throughout my PhD in Electrical and Computer Engineering, also at FEUP, and in association with INESC-TEC.
Having completed my PhD thesis, Generation of Custom Run-time Reconfigurable Hardware for Transparent Binary Acceleration, I am now a post-doc researcher with INESC-TEC on the topic of special compilers for hardware, and also an Auxiliary Assistant Professor with the Department of Informatics at FEUP.
Projects
Publications
A DSL and MLIR Dialect for Streaming and Vectorisation
da Silva, MC;Sousa, L;Paulino, N;Bispo, J;
2024
APPLIED RECONFIGURABLE COMPUTING. ARCHITECTURES, TOOLS, AND APPLICATIONS, ARC 2024
Vision-Radio Experimental Infrastructure Architecture Towards 6G
Teixeira, FB;Ricardo, M;Coelho, A;Oliveira, HP;Viana, P;Paulino, N;Fontes, H;Marques, P;Campos, R;Pessoa, LM;
2024
CoRR
Generation of Custom Run-Time Reconfigurable Hardware for Transparent Binary Acceleration
Cardanha Paulino, NM;
2016
From Instruction Traces to Specialized Reconfigurable Arrays
Bispo, J;Cardanha Paulino, NM;Cardoso, JMP;Ferreira, JC;
2011
2011 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2011, Cancun, Mexico, November 30 - December 2, 2011
Supervised Theses
Dynamically Reconfigurable Multi-Classifier Architecture on FPGA
Joana Lima Macedo
M - 2020
UP-FEUP
Run-Time Selection of Customized Accelerators
José Miguel Carvalho Martins de Campos
M - 2020
UP-FEUP
Dynamically Reconfigurable Multi-Classifier Architecture on FPGA
Joana Macedo
M - 2020
UP-FEUP
Vehicle Tracking in Warehouses via Bluetooth Beacon Angle-of-Arrival
Telmo Francisco da Costa Soares
M - 2020
UP-FEUP
