João Canas Ferreira

I received the Ph.D. degree in Electrical and Computer Engineering from the University of Porto (Portugal) in 2001. I 'm currently an assistant professor with the Faculty of Engineering, University of Porto, and a senior researcher at INESC TEC. I'm a member of IEEE, ACM and Euromicro.

My research interests center around the design of dedicated digital systems for complex and demanding embedded applications. I'm particularly interested in three areas:

Some concrete research topics are:

Domains

Telecommunications and Multimedia Computer Science and Engineering

Projects

iBROW

iBROW aims at developing a novel, low-cost, energy-efficient and compact ultra-broadband short-range wireless communication transceiver, capable of addressing future network usage requirements. This will be pursued using Resonant Tunnelling Diode (RTD) devices which are the fastest pure solid-state electronic devices operating at room temperature, with reported working frequencies exceeding 1 THz. By developing a unified technology that can be integrated into both ends of the wireless link, namely consumer portable devices and fibre-optic supported base-stations, the project aims at increasing the RTD output power, optical detection efficiency and energy efficiency at target frequencies, enabling high-speed short-range wireless communications.

Innovative ultra-BROadband ubiquitous Wireless communications through terahertz transceivers

PEPCC

The domains of embedded systems (ES) and high-performance computing (HPC) are usually seen as distant, but some of their requirements are converging: a modern ES runs complex algorithms with high computational power; the power consumption of ever larger HPC systems requires new levels of power efficiency ("green computing"). Both domains are gaining importance for the society as a whole and for the individual citizens,: complex embedded systems (including cyber-physical systems) have tangible impact on human well-being, natural resource management (smart homes, intelligent transportation) and industrial capabilities, while HPC systems are used to extract new knowledge from the mass of information acquired by ES and provide innovative services both to enterprises (including small and medium ones) and individuals (ranging from traffic management to computer-aided drug discovery). ES have adopted heterogeneous architectures, often based on reconfigurable accelerators like FPGAs or Coarse-Grained Reconfigurable Arrays (CGRAs), because they combine hardware specialization (improving performance and power efficiency) with adaptability at run-time. A similar trend towards heterogeneity is observed in HPC systems with GPUs as accelerators: HPC stakeholders have identified several challenges related to auto-tuning and self adapting systems, and power-aware resource management, matching the trends identified by ES stakeholders on the relevance of heterogeneous accelerators. Many applications in HPC and ES have a small number of regular computational kernels that account for most of the execution time and energy consumption. The manual introduction of reconfigurable accelerators requires significant design time and hardware expertise. It is vital to not compromise developer productivity by requiring manual hardware development and source code alterations. Therefore, this project focuses on approaches that only require knowledge about the program binary code and its runtime behavior. The goal of this project is to devise efficient techniques for dynamically mapping computations extracted from execution behavior to the resources of specialized reconfigurable accelerators. The techniques will identify at runtime the hotspots of program execution. They are then optimized and mapped to CGRAs tailored to the actual set of executing kernels. Whenever one hotspot needs to be executed, the accelerator is transparently invoked. The use of specialized CGRAs reduces resource usage and improves performance. The project will apply these concepts in the ES and HPC domains. Expected achievements include important performance improvements over CPU-based computation in the system (at least 3x on average), while maintaining almost the same energy consumption. The project expects to reduce energy consumption by at least 30% through reduction of the clock frequency of the CPU, while still matching the performance of the system without accelerator.

Power efficiency and performance for embedded and HPC systems with custom CGRAs

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Publications

AN IC ARCHITECTURE FOR BOARD-LEVEL MIXED-SIGNAL TEST SUPPORT

FERREIRA, JC;LEAO, AC;DASILVA, JM;MATOS, JS;

1994

7TH MEDITERRANEAN ELECTROTECHNICAL CONFERENCE, VOLS 1-3

Mixed hardware/software applications on dynamically reconfigurable hardware

Ferreira, JC;Matos, JS;

1998

5th IEEE International Conference on Electronics, Circuits and Systems, ICECS 1998, Surfing the Waves of Science and Technology, Lisbon, Portugal, September 7-10, 1998

From Instruction Traces to Specialized Reconfigurable Arrays

Bispo, J;Cardanha Paulino, NM;Cardoso, JMP;Ferreira, JC;

2011

2011 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2011, Cancun, Mexico, November 30 - December 2, 2011

A routing protocol for WSN based on the implementation of source routing for minimum cost forwarding method

Derogarian, F;Ferreira, JC;Tavares, VMG;

2011

SENSORCOMM 2011 - 5th International Conference on Sensor Technologies and Applications and WSNSCM 2011, 1st International Workshop on Sensor Networks for Supply Chain Management

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Supervised theses

Tangible language for educational programming of robots and other targets

Ângela Filipa Pereira Cardoso

M - 2019

UP-FEUP

Centres

Telecommunications and Multimedia

The Centre for Telecommunications and Multimedia (CTM) welcomes close to 200 members, including at least 100 integrated researchers who carry out scientific work in the fields of communications, Artificial Intelligence, and computer science and engineering. The Centre’s activities cover several Research and Development (R&D) domains: Communications and Electronics Radio Frequency Technologies Optoelectronics Microelectronics Wireless Communication Networks Computer Perception Computer Vision applied to Medical Imaging Computer Vision applied to Digital Media Computer Audio applied to Music With multidisciplinary teams that include dozens of PhDs, CTM is strongly committed to both European and national research projects, as well as consultancy projects with industry.